According to the Gizchina website, the company the three new SoCs carry the catchy titles of MT6739, MT6750 and MT6750T. .

The MT6739 will probably replace the MT6735. Both have quad A53 cores but it will mean that the MT6739 will get a Cat 6 upgrade from Cat 4. The MT6739 supports speeds of up to 1.5GHz, 512 KB L2 cache, 1280×720 at 60fps resolution, and video decode to 1080p 30fps with H.264 and 13 megapixel camera. This means it is an entry level SoC for phones that might fit into the $100 price range.

The MT6750 and MT6750T look like twins, only the T version supports full HD 1920×1080 displays. The MT6750 has eight cores, four A53 clocked at 1.5Ghz and four A53 clocked at 1.0GHz and is manufactured on TSMC’s new 28nm High Performance Mobile Computing manufacturing mode. This is the same manufacturing process MediaTek is using for the Helio P10 SoC. The new process allows lower leakage and better overall transistor performance at lower voltage.

The MT6750 SoC supports single channel LPDDR3 666MHz and eMCP up to 4GB. The SoC supports eMMC 5.1, 16 megapixel camera, 1080p 30 fps with both H.264 and H.265 decoding. It comes with an upgraded ARM Mali T860 MP2 GPU with 350 MHz and display support of 1280×720 HD720 ready with 60 FPS. This means the biggest upgrade is the Cat 6 upgrade and it makes sense – most of European and American networks now are demanding a Cat 6 or higher modem that supports carrier aggregation.

This new SOc looks like a slowed down version of Helios P10 and should be popular for entry level Android phones.

Courtesy-Fud

Samsung’s new HBM solution will be used in high-performance computing (HPC), advanced graphics, network systems and enterprise servers, and is said to offer DRAM performance that is “seven times faster than the current DRAM performance limit”.

This will apparently allow faster responsiveness for high-end computing tasks including parallel computing, graphics rendering and machine learning.

“By mass producing next-generation HBM2 DRAM, we can contribute much more to the rapid adoption of next-generation HPC systems by global IT companies,” said Samsung Electronics’ SVP of memory marketing, Sewon Chun.

“Also, in using our 3D memory technology here, we can more proactively cope with the multifaceted needs of global IT, while at the same time strengthening the foundation for future growth of the DRAM market.”

The 4GB HBM2 DRAM, which uses Samsung’s 20nm process technology and advanced HBM chip design, is specifically aimed at next-generation HPC systems and graphics cards.

“The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8Gb core dies on top. These are then vertically interconnected by TSV holes and microbumps,” explained Samsung.

“A single 8Gb HBM2 die contains over 5,000 TSV holes, which is more than 36 times that of an 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.”

Samsung’s new DRAM package features 256GBps of bandwidth, which is double that of an HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips.

The firm’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb GDDR5-based solution, and embeds error-correcting code functionality to offer high reliability.

Samsung plans to produce an 8GB HBM2 DRAM package this year, and by integrating this into graphics cards the firm believes designers will be able to save more than 95 percent of space compared with using GDDR5 DRAM. This, Samsung said, will “offer more optimal solutions for compact devices that require high-level graphics computing capabilities”.

Samsung will increase production volume of its HBM2 DRAM over the course of the year to meet anticipated growth in market demand for network systems and servers. The firm will also expand its line-up of HBM2 DRAM solutions in a bid to “stay ahead in the high-performance computing market”.

Courtesy-TheInq

Based on the firm’s fourth generation Graphics Core Next (GCN) architecture and built using a 14nm FinFET fabrication process, the upcoming architecture is a big jump from the current 28nm process.

AMD said that it expects shipments of Polaris GPUs to begin in mid-2016, offering improvements such as HDR monitor support and better performance-per-watt.

The much smaller 14nm FinFET process means that Polaris will deliver “a remarkable generational jump in power efficiency”, according to AMD, offering fluid frame rates in graphics, gaming, virtual reality and multimedia applications running on small form-factor thin and light computer designs.

“Our new Polaris architecture showcases significant advances in performance, power efficiency and features,” said AMD president and CEO Lisa Su. “2016 will be a very exciting year for Radeon fans driven by our Polaris architecture, Radeon Software Crimson Edition and a host of other innovations in the pipeline from our Radeon Technologies Group.”

The Polaris architecture features AMD’s fourth-generation GCN architecture, a next-generation display engine with support for HDMI 2.0a and DisplayPort 1.3, and next-generation multimedia features including 4K h.265 encoding and decoding.

GCN enables gamers to experience high-performance video games with Mantle, a tool for alleviating CPU bottlenecks such as API overhead and inefficient multi-threading. Mantle, which is basically AMD’s answer to Microsoft’s Direct X, enables improvements in graphics processing performance. In the past, AMD has claimed that Kaveri teamed with Mantle to enable it to offer built-in Radeon dual graphics to provide performance boosts ranging from 49 percent to 108 percent.

The new GPUs are being sampled to OEMs at the moment and we can expect them to appear in products by mid-2016, AMD said. Once they are in the market, we can expect to see much thinner form factors in devices thanks to the much smaller 14nm chip process.

Courtesy-TheInq

According to Ars Technica Under the handle “GPUOpen” AMD is releasing a slew of open-source software and tools to give developers of games, heterogeneous applications, and HPC applications deeper access to the GPU and GPU resources.

In a statement AMD said that as a continuation of the strategy it started with Mantle, it is giving even more control of the GPU to developers.

“ As console developers have benefited from low-level access to the GPU, AMD wants to continue to bring this level of access to the PC space.”

The AMD GPUOpen initiative is meant to give developers the ability to use assets they’ve already made for console development. They will have direct access to GPU hardware, as well as access to a large collection of open source effects, tools, libraries and SDKs, which are being made available on GitHub under an MIT open-source license.

AMD wants GPUOpen will enable console-style development for PC games through this open source software initiative. It also includes an end-to-end open source compute infrastructure for cluster-based computing and a new Linux software and driver strategy

All this ties in with AMD’s Boltzmann Initiative and an HSA (Heterogeneous System Architecture) software suite that includes an HCC compiler for C++ development. This was supposed to open the field of programmers who can use HSA. A new HCC C++ compiler was set up to enable developers to more easily use discrete GPU hardware in heterogeneous systems.

It also allows developers to convert CUDA code to portable C++. According to AMD, internal testing shows that in many cases 90 percent or more of CUDA code can be automatically converted into C++ with the final 10 percent converted manually in the widely popular C++ language. An early access program for the “Boltzmann Initiative” tools is planned for Q1 2016.

AMD GPUOpen includes a new Linux driver model and runtime targeted at HPC Cluster-Class Computing. The headless Linux driver is supposed to handle high-performance computing needs with low latency compute dispatch and PCI Express data transfers, peer-to-peer GPU support, Remote Direct Memory Access (RDMA) from InfiniBand that interconnects directly to GPU memory and Large Single Memory Allocation support.

Most of the entry level, mainstream and even performance graphics cards from both Nvidia and AMD will rely on the GDDR5. This memory has been with us since 2007 but it has dramatically increased in speed. The memory chip has shrunken from 60nm in 2007 to 20nm in 2015 making higher clocks and lower voltage possible.

Some of the big boys, including Samsung and Micron, have started producing 8 Gb GDDR5 chips that will enable cards with 1GB memory per chip. The GTX 980 TI has 12 chips with 4 Gb support (512MB per chip) while Radeon Fury X comes with four HMB 1.0 chips supporting 1GB per chip at much higher bandwidth. Geforce Titan X has 24 chips with 512MB each, making the total amount of memory to 12GB.

The next generation cards will  get 12GB memory with 12 GDDR5 memory chips or 24GB with 24 chips. Most of the mainstream and performance cards will come with much less memory.

Only a few high end cards such as Greenland high end FinFET solution from AMD and a Geforce version of Pascal will come with the more expensive and much faster HMB 2.0 memory.

GDDR6 is arriving in 2016 at least at Micron and the company promises a much higher bandwidth compared to the GDDR5. So there will be a few choices.

Source-http://www.thegurureview.net/computing-category/will-gddr5-rule-in-2016.html

VR-World says that stage one results are finished and where shown off this week at SC15. This included a Heterogeneous Compute Compiler (HCC); a headless Linux driver and HSA runtime infrastructure for cluster-class, High Performance Computing (HPC); and the Heterogeneous-compute Interface for Portability (HIP) tool for porting CUDA-based applications to C++ programming.

AMD hopes the tools will drive application performance from machine learning to molecular dynamics, and from oil and gas to visual effects and computer-generated imaging.

Jim Belak, co-lead of the US Department of Energy’s Exascale Co-design Center in Extreme Materials and senior computational materials scientist at Lawrence Livermore National Laboratory said that AMD’s Heterogeneous-compute Interface for Portability enables performance portability for the HPC community.

“The ability to take code that was written for one architecture and transfer it to another architecture without a negative impact on performance is extremely powerful. The work AMD is doing to produce a high-performance compiler that sits below high-level programming models enables researchers to concentrate on solving problems and publishing groundbreaking research rather than worrying about hardware-specific optimizations.”

The new AMD Boltzmann Initiative suite includes an HCC compiler for C++ development, greatly expanding the field of programmers who can leverage HSA.

The new HCC C++ compiler is a key tool in enabling developers to easily and efficiently apply the hardware resources in heterogeneous systems. The compiler offers more simplified development via single source execution, with both the CPU and GPU code in the same file.

The compiler automates the placement code that executes on both processing elements for maximum execution efficiency.

Source- http://www.thegurureview.net/computing-category/amd-appears-to-be-pushing-its-boltzmann-plan.html

Over the last few months both have been busy with new releases. Nvidia has its GeForce GTX 950 and GTX 980 Ti, while AMD put its first HBM-powered cards in the Radeon R9 Fury X, Fury and the super-small R9 Nano into the shops.

According to JPR, overall GPU shipments are up quarter-over-quarter – with AMD’s overall GPU shipments up 15.8 per cent. But before AMD fanboys get all excited by a surprise return to form from AMD, JPR said that that NVIDIA “had an exceptionally strong quarter”. Nvidia saw an uptick of 21.3 per cent.

The PC market as a whole increased by 7.5 per cent quarter-over-quarter but decreased 9 per cent year-over-year. Nivida’s discrete GPU shipments were up 26.3 per cent according to JPR, while AMD’s discrete GPUs spiked by 33 per cent.

AMD’s mobile GPU shipments for notebooks increased by 17 per cent, while NVIDIA had 14 per cent.

Designed for demanding embedded needs, the processors incorporate the newest AMD 64-bit x86 CPU core (“Excavator”), plus third-generation Graphics Core Next GPU architecture, and better power management for reduced energy consumption.

AMD tells us that combined, these chips provide industry-leading graphics performance and key embedded features for next-generation designs. The SOC architecture enables simplified, small form factor board and system designs from AMD customers and a number of third party development platform providers.

What AMD brings to the party is its graphics and multimedia performance, including capability for hardware-accelerated decode of 4K video playback and support for the latest DDR4 memory.
Jim McGregor, principal analyst, TIRIAS Research said that AMDs push into x86 embedded platforms is paying off with an increasing number of customers and applications.

“There is a need for immersive graphics, high-quality visualization, and parallel computing in an increasing number of embedded applications. Across these fronts, the AMD Embedded R-Series SOC is a very compelling solution.”

Scott Aylor, corporate vice president and general manager, AMD Embedded Solutions said that his outfit’s AMD Embedded R-Series SOC is a strong match for these needs in a variety of industries including digital signage, retail signage, medical imaging, electronic gaming machines, media storage, and communications and networking.

“The platform offers a strong value proposition for this next generation of high-performance, low-power embedded designs.”

The new AMD Embedded R-Series SOCs offer 22 percent improved GPU performance when compared to the 2nd Generation AMD Embedded R-Series APU2 and a 58 percent advantage against the Intel Broadwell Core i7 when running graphics-intensive benchmarks.

AMD released some of the specs for its integrated AMD Radeon graphics including:

Up to eight compute units4 and two rendering blocks

GPU clock speeds up to 800MHz resulting in 819 GFLOPS

•DirectX 12 support

Fully HSA Enabled

The AMD Embedded R-Series SOC was architected with embedded customers in mind and includes features such as industrial temperature support, dual-channel DDR3 or DDR4 support with ECC (Error Correction Code), Secure Boot, and a broad range of processor options.

It has a configurable thermal design power (cTDP) allows designers to adjust the TDPs from 12W to 35W in 1W increments for greater flexibility.

The SOC also has a 35 percent reduced footprint when compared to the 2nd Generation AMD Embedded R-Series APU, making it an excellent choice for small form factor applications.

AMD said that the range is the first embedded processor with dual-channel 64-bit DDR4 or DDR3 with Error-Correction Code (ECC), with speeds up to DDR4-2400 and DDR3-2133, and support for 1.2V DDR4 and 1.5V/1.35V DDR3.

Its dedicated AMD Secure Processor supports secure boot with AMD Hardware Validated Boot (HVB) and initiates trusted boot environment before starting x86 cores
It has a high-performance Integrated FCH featuring PCIe Gen3 USB3.0, SATA3, SD, GPIO, SPI, I2S, I2C, and UART

The AMD Embedded R-Series SOC provides industry-leading ten-year longevity of supply. The processors support Microsoft Windows 7, Windows Embedded 7 and 8 Standard, Windows 8.1, Windows 10, and AMD’s all-open Linux driver including Mentor Embedded Linux from Mentor Graphics and their Sourcery CodeBench IDE development tools.

It will be interesting to see if AMD can make up the ground it has lost on PCs and higher ticket items. Most of the company still appears to be in a holding pattern until Zen arrives.

Courtesy-http://www.thegurureview.net/computing-category/will-amds-newest-soc-save-the-company.html

The outfit has been going through hell lately. Last month AMD ace CPU architect Jim Keller stepped away from the company after completing his work on Zen.

Rogers was one of AMD’s high-ranking technology and engineering corporate fellows, and been responsible for helping to develop the software ecosystem behind AMD’s heterogeneous computing products and the Heterogeneous System Architecture.

He was a public figure for AMD and active on the software development and evangelism side, frequently presenting the latest HSA tech and announcements for AMD at keynotes and conferences.

While he is not the only person working on the software side of HSA at AMD, Rogers’ role in its development is important. Rogers was a major contributor to the HSA Foundation, helping to initially found it in 2012. He served as the Foundation’s president until he left AMD.

It seems his defection was kept secret, and took place sometime this quarter and did not manage to leak.

According to his LinkedIn profile Phil Rogers is now Nvidia’s “Chief Software Architect – Compute Server” which is similar to what he was doing over at AMD. Nvidia is not a member of the HSA Foundation, but they are currently gearing up for the launch of the Pascal GPU family, which has some features that overlap well with Phil Rogers’ expertise.

Pascal’s NVLink CPU & GPU interconnect would allow tightly coupled heterogonous computing similar to what AMD has been working on. It makes a fair bit of sense for Nvidia to bring over a heterogeneous compute specialist makes a great deal of sense.

Rogers’ departure from AMD will have to be mentioned on the earnings call on the 15th. AMD’s Gregory Stoner will probably replace him. Stoner is AMD’s current Senior Director of Compute Solutions Technology and long-time Vice President of the HSA Foundation.

Source-http://www.thegurureview.net/computing-category/is-amd-losing-top-scientist-to-nvidia.html